Verilog

A HDL that is:

• Weakly typed
• Concise
• Deterministic
• C-like System Verilog is the better version of verilog.

Installation/Setup

1. With VSCode, install
2. yay -S iverilog
3. yay -S gtkwave

Simulating .v File

1. Write the .v file
2. iverilog -o output.vpp input.v
3. vpp output.vpp
4. gtkwave output.vcd

Concepts

• Verilog Module
• Verilog Combinational Sequence
• Verilog Sequential Sequence
• Verilog Datatypes
• Verilog Literals
• Verilog Array
• Verilog Block
• Verilog Operators
• Verilog Wire
• Verilog Reg
• Verilog logic
• Verilog Assignment
• Verilog Concatenation
• Verilog Conditionals
• Verilog Ternary Operator
• Verilog Case Statement

Guides

• Verilog AND Gate
• Verilog OR Gate
• Verilog NAND Gate
• Verilog NOR Gate
• Verilog XOR Gate
• Verilog XNOR Gate
• Verilog NOT Gate
• Verilog 4-Bit Adder
• Verilog D Flip Flop

Boilerplate

module module_name(){
	input A;
	output B;
	assign B = !A;
}
endmodule