A modified D Flip-Flop that attempts to replicate the SR Flip Flop.
- Set
- Reset
Can be set as: - synchronous mode (controled by Clock Signal)
- asynchronous mode (state is independent of clock)
Circuit Diagram
Truth Table
| Output | ||
|---|---|---|
| 0 | 0 | maintain output |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | Toggle |